MCLKQ_CLOCK_DIV=DIVBY1, CLK_CLOCK_DIV=DIVBY1
Clock control
| CLK_CLOCK_DIV | PDM CLK (FPDM_CLK) (1st divider): This configures a frequency of PDM CLK. The configured frequency is used to operate PDM core. I.e. the frequency is input to MCLKQ_CLOCK_DIV register. Note: configure a frequency of PDM CLK as lower than or equal 50MHz with this divider. 0 (DIVBY1): Divide by 1 1 (DIVBY2): Divide by 2 (no 50 percent duty cycle) 2 (DIVBY3): Divide by 3 (no 50 percent duty cycle) 3 (DIVBY4): Divide by 4 (no 50 percent duty cycle) |
| MCLKQ_CLOCK_DIV | MCLKQ divider (2nd divider) (Note: These bits are connected to AR36U12.PDM_CORE2_CFG.DIV_MCLKQ) 0 (DIVBY1): Divide by 1 1 (DIVBY2): Divide by 2 (no 50 percent duty cycle) 2 (DIVBY3): Divide by 3 (no 50 percent duty cycle) 3 (DIVBY4): Divide by 4 (no 50 percent duty cycle) |
| CKO_CLOCK_DIV | PDM CKO (FPDM_CKO) clock divider (3rd divider): FPDM_CKO = MCLKQ / (CKO_CLOCK_DIV + 1) Note: To configure ‘0’ to this field is prohibited. (Note: PDM_CKO is configured by MCLKQ_CLOCK_DIV, CLK_CLOCK_DIV and CKO_CLOCK_DIV. ) (Note: These bits are connected to AR36U12.PDM_CORE_CFG.MCLKDIV) |
| SINC_RATE | SINC Decimation Rate. For details, see the data sheet provided by Archband. Oversampling Ratio = Decimation Rate = 2 X SINC_RATE (Note: These bits are connected to AR36U12.PDM_CORE_CFG.SINC_RATE) |